1. Field
The present disclosure relates generally to integrated circuits, and more particularly, to memory with a multiple word line design.
2. Background
Memory may include bit cells arranged in rows and columns. Each row may include many bit cells. Each bit cell may include a number of transistors arranged in various configurations. Separate read and write word lines may perform read and write operations, respectively. During a read operation, existing designs may use a single read word line. When a read word line connected to a bit cell is asserted, the read bit line connected to that bit cell may discharge. When the read bit line discharges, the read bit line must subsequently be re-charged for the next read operation.
There exist circumstances where it is not necessary to read data stored in every bit cell in a particular row. As such, it may not always be necessary to discharge the read bit line of every bit cell in that particular row of bit cells. When the read bit line connected to bit cells that do not need to be read is needlessly discharged, that read bit line needs to be re-charged for the next read operation. Power is consumed to perform this re-charge.